Recently, the usage of non-volatile memory comprising a semiconductor device capable of rewriting data and retaining data stored therein even while the device is un-powered has become increasingly popular. Flash memory is one example of non-volatile memory. A typical flash memory is disposed with a transistor which operates as a memory cell and includes a floating gate or an insulating film called a charge storage layer for accumulating electrons used to store data. Flash memory with a SONOS (Silicon Oxide Nitride Oxide Silicon) structure for accumulating the electrons in a trap layer of an ONO (Oxide Nitride Oxide) film has been introduced as a flash memory using an insulating film as the charge storage layer.
U.S. Pat. No. 6,011,725 discloses a SONOS structured flash memory having a virtual ground memory cell which is symmetrically operated by switching between a source and a drain. In this flash memory, a bit line which serves as a source and a drain is formed in a semiconductor substrate and electric charges can be stored in a trap layer in an ONO film formed on the semiconductor substrate. By switching between the source and the drain, two charge storage regions can be formed in a single memory cell.
Japanese Patent Application Publication No. JP-A-2005-57187 discloses a technology to form a metal silicide layer on a bit line by forming a spacer in an ONO film.
FIG. 1A is an illustration of a conventional flash memory and is a cross-sectional view taken along a word line, i.e. a gate. According to FIG. 1A, bit lines 30 are formed in a semiconductor substrate 10. A first silicon oxide film 12 that is a tunnel oxide film, a trap layer 14a, and a second silicon oxide film 18 that is a top oxide film are disposed on the semiconductor substrate 10 as an ONO film 20a. A word line 32 is disposed on the ONO film 20a. On both sides of each of the bit lines 30 in the trap layer 14a, electric charges 58 are stored. However, since the trap layer 14a is also formed on the bit line 30, electric charges are diffused onto the bit line 30 along the direction as indicated in FIG. 1A. Therefore, electric charges on a channel, i.e. between the bit lines 30 of the semiconductor substrate 10, are reduced. The threshold voltage of a transistor which configures a memory cell is determined by the electric charges on the channel. Consequently, even when electric charges are stored in the trap layer 14a, the electric charges which do not contribute to the threshold voltage of the transistor will increase.
FIG. 1B is an alternate illustration of a conventional flash memory and is a cross-sectional view in the neighborhood of a plug metal coupled to the bit line. With reference to FIG. 1B, the bit line 30 is formed in the semiconductor substrate 10, the ONO film 20a is disposed on the semiconductor substrate 10, and an interlayer insulation film 40 is disposed on the ONO film 20a. A plug metal 38 coupled to the bit line 30 is disposed in the interlayer insulation film 40. A wiring layer 42 is coupled to the plug metal 38, and a protective film 44 is disposed on the interlayer insulation film 40. The plug metal 38 is directly coupled to the bit line 30 that is an n-type semiconductor. Therefore, a contact resistance between the plug metal 38 and the bit line 30 becomes high.
If a metal silicide layer is disposed between the bit line 30 and the plug metal 38, the contact resistance between the plug metal 38 and the bit line 30 can be reduced. However, when the metal silicide layer is also formed on the semiconductor substrate 10, the semiconductor substrate 10 that is a p-type semiconductor and the bit line 30 that is an n-type semiconductor are electrically coupled. Therefore, the metal silicide layer is required to be disposed only on the bit line 30. For this purpose, an opening in the ONO film 20a is required to be disposed by using an exposure technology. Unfortunately, disposing an opening only in the ONO film 20a on the fine bit line 30 can be difficult.